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Future Technology Devices International Ltd.
MORPH-IC-II Datasheet
Document Reference No.: FT_000198 Version 1.02 Issue Date: 2010-08-20
MORPH-IC-II is a compact, yet powerful FPGA module which is capable of synthesising LSI (Large Scale Integration) designs using the embedded Altera Cyclone-II FPGA. Communication between the FPGA and a PC is carried out via the FTDI FT2232H, a USB 2.0 Hi-Speed (480Mbit/s) USB bridge. Sub-100ms FPGA programming/re-programming makes MORPH-IC-II ideal for applications which require users to reconfigure hardware functionality on-the-fly by downloading new software over USB : "morphing" the hardware. MORPH-IC-II has increased in capability and processing power from a previous FTDI FPGA module called MorphIC-1K.
Future Technology Devices International Ltd (FTDI) Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow, G41 1HH, United Kingdom Tel.: +44 (0) 141 429 2777 Fax: + 44 (0) 141 429 2758
E-Mail (Support): support1@ftdichip.com Web: http://www.ftdichip.com
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminar y information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow, G41 1HH, United Kingdom. Scotland Registered Number: SC136640
Copyright (c) 2010 Future Technology Devices International Limited

Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
1
Introduction
MORPH-IC-II is a compact and powerful FPGA module which is capable of implementing LSI (Large Scale Integration) designs or entry level VLSI (Very Large Scale Integration) designs. Designs can be synthesised through utilising up to 4,608 Logic Elements of MORPH-IC-IIs on board FPGA. The MORPH-IC-II platform combines an Altera Cyclone(R)-II FPGA with high-performance USB 2.0 capabilities that facilitate Hi-speed communications with ultra-fast, sub-100ms FPGA programming/reprogramming. This makes MORPH-IC-II ideal for applications which require users to reconfigure hardware functionality on-the-fly by downloading new software over USB : "morphing" the hardware. Communication between the FPGA and the PC is done through a USB 2.0 connection to the FTDI FT2232H USB 2.0 Hi-Speed (480Mbit/s) USB bridge. MORPH-IC-II is an easy to use module which allows users to program and interact with the FPGA using a free software package produced by Altera called Quartus II. This datasheet describes the following: - Features and applications of MORPH-IC-II - The pin configuration - Mechanical details - User guide - Schematic details - EEPROM default setting MORPH-IC-II is fully backward compatible with the MorphIC-1K module (the predecessor of MORPH-IC-II). The MorphIC-1K is an FPGA/USB module used in medium scale production as an alternative to producing an ASIC and prototyping. MORPH-IC-II is an upgraded version of the MorphIC-1K with increased capacity and increased speed. MORPH-IC-II is a plug in replacement for the MorphIC-1K, but MORPH-IC-II has additional I/Os. For new applications, it is recommended to design any application board for the MorphIC-II header configuration to utilize the additional 40 I/Os and the JTAG signal ports of the header. Although MORPH-IC-II is fully backward compatible with MorphIC-1K, there are some differences. For example, MORPH-IC-II uses Port A for the FIFO interface rather than Port B. MORPH-IC-II has some additional features over MorphIC-1K such as being able to operate some I/Os at various logic voltage levels. For example the I/O can be operated at 1.5V/1.8V/2.5V/3.3V. This provides added flexibility to the designer. MORPH-IC-II is shown in Fig. 1. The module has 4 connectors giving access to all the FPGA I/Os plus a JTAG header, that can be used to interface to MORPH-IC-II with SignalTap Analyser (a function included in the Quartus-II package). SignalTap can be used to display the waveform of every pin of the FPGA. MORPH-IC-II interfaces to a PC through a USB Type B connector. Two LEDs indicate when the board is powered and when the FPGA is programmed.
Fig. 1 - The MORPH-IC-II Copyright (c) 2010 Future Technology Devices International Limited 1

Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
Table of Contents 1 2 3 Introduction............................................................................................ 1
1.1 Applications ......................................................................................................... 3
Features ................................................................................................. 4
2.1 Driver Support ..................................................................................................... 4
Functional Description .......................................................................... 5
3.1 3.2 MORPH-IC-II Block Diagram.................................................................................. 5 Getting Started..................................................................................................... 6
Configuring the Jumper settings....................................................................................... 6 Configuring the FPGA .......................................................................................................... 6
3.2.1 3.2.2
3.3 3.4 3.5
3.5.1
MORPH-IC-II Signal Levels Supported. ................................................................ 7 MORPH-IC-II Header Connections. ....................................................................... 8 MORPH-IC-II Hardware Configuration ................................................................ 14
Communications and Programming Interfaces of MORPH-IC-II .............................................. 14 GPIO Connections .............................................................................................................. 16 MORPH-IC-II JTAG Connections ....................................................................................... 16 Pin-Map Configuration....................................................................................................... 17
3.5.2 3.5.3 3.5.4
4 5
MorphIO-II - An Application Software ................................................ 18 Electrical Details .................................................................................. 20
5.1 5.2 Absolute Maximum Ratings.............................................................................. 20 Recommended Opperating Conditions ........................................................... 20
6 7
Mechanical Details .............................................................................. 22 Contact Information............................................................................. 23
Appendix A - FT2232H EEPROM Configuration........................................................ 24 Appendix B - Revision History ................................................................................... 25 Appendix C - Schematic Drawings ............................................................................ 26 Appendix D - Assembly Drawings .............................................................................. 29
Copyright (c) 2010 Future Technology Devices International Limited
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
1.1 Applications
Possible applications:
ASIC prototyping using USB connectivity to FPGA. Providing a fast and easy alternative to ASIC solutions for low to medium volumes of product. Academic FPGA design exercise - ideal for learning and experimenting with HDL (Hardware Design Language) Digital signal processing Audio/Video Cryptography
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
2
Features
MORPH-IC-II has the following features: FT2232HQ Dual, Hi-Speed USB UART/FIFO IC used for USB communications Altera Cyclone 2 - EP2C5F256C8N FPGA capable of synthesizing large scale integrated circuits Ultra fast FPGA configuration/reconfiguration over USB (under 0.1 sec) 4,608 Embedded FPGA Logic Elements (about 80,000 Gates typically) 26 Embedded Logic RAM Elements (119Kbits) FPGA-PC USB Data Transfer at up to 40M Byte/sec Onboard 93LC56B configuration EEPROM MOSFET switched 5V and 3.3V power outputs for powering external logic Onboard 12MHz crystal and essential support components for FT2232HQ 80 dedicated external I/O pins Onboard 50MHz oscillator as FPGA primary clock - also available for external use. JTAG interface for testing the I/Os and registers of the FPGA 1 dedicated external clock input Powered from USB bus or external PSU Standard 0.1 inch pitch format connector pins, ideal for rapid prototyping or small-medium size production runs FTDI's VCP and D2XX USB Windows and Linux USB drivers (provided) eliminate the need for driver development in most cases Windows FPGA loader interface DLL supplied including interface examples in VB, VC++ and Delphi Stand-alone FPGA loader programs provided for Windows and Linux VHDL programming examples (I/O over USB) provided Delphi application software examples including source code provided Free Altera Quartus II Software Starter Suite development software available from the Altera Website Backward compatible with the existing MorphIC-I Supports 1.5/1.8/2.5/3.3-V LVTTL/LVCMOS signals, IOBANK1-3 restricted to 3.3V.
2.1 Driver Support
MORPH-IC-II uses the FTDI Ft2232H USB bridge chip. This chip requires USB drivers which can be downloaded free of charge from http://www.ftdichip.com/FTDrivers.htm.
Royalty free VIRTUAL COM PORT (VCP) DRIVERS for... Windows 2000, Server 2003, XP Server 2008 Windows XP and XP 64-bit Windows Vista and Vista 64-bit Windows 7 Windows XP Embedded Windows CE 4.2, 5.0, 5.2 and 6.0 Mac OS-X Linux (2.6.9 or later)
Royalty free D2XX Direct Drivers (USB Drivers + DLL S/W Interface) Windows 2000, Server 2003, Server 2008 Windows XP and XP 64-bit Windows Vista and Vista 64-bit Windows 7 Windows XP Embedded Windows CE 4.2, 5.0, 5.2 and 6.0 Linux (2.4 or later) and Linux x86_64
The utilities included MORPH-IC-II package can run on Windows 2000, ME, XP, Vista and 7. The recommend design utility for MORPH-IC-II is Quartus-II. This free software can be downloaded from the Altera website: http://www.altera.com.
Copyright (c) 2010 Future Technology Devices International Limited 4

Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
3
Functional Description
3.1 MORPH-IC-II Block Diagram
A block diagram of the MORPH-IC-II is given in Fig. 2. MORPH-IC-II module can be USB powered or self powered. The power mode is selected using the "VBUS" jumper - as indicated on the diagram below. The FPGA can be programmed from a PC via the USB interface and the FT2232H USB bridge. FT2232H requires a 12MHz crystal and an external EEPROM which is used to configure FT2232H. The Altera FPGA is powered from a +3.3V regulator supply with the exception of its internal PLLs which are powered by a +1.2V regulated supply. The power supply to the FPGA is disabled, using the MOSFET switch, when FT2232H is in power save mode. The I/Os of the FPGA are partitioned into 4 I/O banks. These banks each have their own power connection. The voltage of the power connection to each bank defines the voltage level of the signals of that bank. The power supply to I/O bank 4 is configured differently to add more flexibility. The I/O bank 4 power can be supplied from an external supply to the V_Bank 4 pins on J2 or from the 3V3IO net connected to the on board regulator. This feature allows signals of different voltage levels to be used in an application and is explained with more detail in Section 3.2. MORPH-IC-II uses a 50MHz oscillator which provides the clock source to the FPGA. Alternatively the FPGA can be synchronised to an external clock using the CLKIN pin on connector J2. The four connectors J1, J2, J3 and J4 provide I/O connectivity between MORPH-IC-II and any application board. The connector give a total of 80 signal lines, a FIFO interface capability, power supply pins, an external clock line and an external reset line. The JTAG interface can be accessed through the JTAG port or J3 and J4 connectors, using an Altera Byte Blaster (or equivalent) cable and SignalTap Analyser which is an application of Quartus II the signals of all the I/Os of the FPGA can be displayed on a PC monitor.
VCCUSB
MOSFET POWER SWTICH 3.3V REG
VCCSW 3.3V REG 1.2V REG 1.2DV
3V3IO
V_Bank4
1
IO CONNECTORS
29 30
VCCUSB
2
V_Bank4
17 18
VBUS JUMPER
VCC3V3 PROGRAMMING INTERFACE
VCCSW USB data V_BANK4 3V3IO BANK4_IO
17 18 29 30
3V3IO
USB CONNECTOR
FT2232H USB INTERFACE IC
DATA TRANSFER INTERFACE
ALTERA CYCLONE TWO EP2C5F256C8N FPGA
INT CLOCK EXT CLOCK
BANK4_IO
J1
IO IO
J2
12MHz XTAL
14
93C56 USB CONFIGURATION EEPROM
IO 50MHz OSCILLATOR
12
IO
3V3IO
J3
JTAG PORT JTAG
J4
Fig. 2 - Hardware Representation of the MORPH-IC-II
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
3.2 Getting Started
3.2.1 Configuring the Jumper settings
MORPH-IC-II module has two jumpers labelled VBUS and V_BANK4. 1) Jumper VBUS connects USB connector pin 1 to J1-1. A) When jumper VBUS is closed, the MORPH-IC-II module is powered from the USB bus. This connects the VBUS power from the USB host PC to the voltage regulator input of MORPH-IC-II. This voltage regulator provides power to the following: VCC3V3, VPLL and VUSB all of which power the FT2232H chip. This mode is known as "bus powered mode". B) When jumper VBUS is open, the MORPH-IC-II module requires an external voltage supply of 5 Volts DC applied to J1-1. This mode is known as "self powered mode". 2) Jumper V_BANK4 connects 3V3IO to the power supply pins of Bank 4. A) When jumper V_BANK4 is closed, a short is formed between 3V3IO and V_BANK4. This connection provides 3.3 volts to I/O Bank 4 of the FPGA. NOTE: When this jumper is closed J2-29 and J2-30 must be unconnected or connected to a 3V3 supply (this is the case for typical MorphIC-1K application boards). B) When jumper V_BANK4 is open, an external voltage supply must be applied to J2-29 and J230 to power the I/O Bank 4. The voltage level supplied should match the voltage level of the input signals. A summary of the jumper functions is given in Table 1.
Jumper Name VBUS VBUS V_BANK4
State CLOSED OPEN CLOSED
Description Powered from the USB Bus An external supply needs to be applied via J1-1 3.3V supplied to I/O Bank 4 An external voltage of either 1.5V, 1.8V, 2.5V or
V_BANK4
OPEN
3.3V needs to be applied to I/O Bank 4 via J2-29 and J2-30
Table 1 - Jumper Description
NOTE: When using V_BANK4, care must be taken regarding this jumper; if there is a large enough discrepancy between the voltage that powers an IO Bank and the logic high voltage of the signals processed by the bank damage can occur.
3.2.2 Configuring the FPGA
The MORPH-IC-II package includes a *.RBF loader programme called "MorphLd". This programme is used to load RBF files into the FPGA of MORPH-IC-II via the USB to Passive Serial interface. These *.RBF are synthesised HDL (VHDL or Verilog) code with additional settings for the FPGA specified by the Quartus-II options. These files are generated when a HDL project is compiled using (suitably configured) Quartus-II or a similar HDL compiler. Using this utility along with Quartus-II the HDL code of an application can be compiled and exported to MORPH-IC-II. (See AN_141_MorphIO-II and MorphLd Utilities for MORPH-IC-II)
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
3.3 MORPH-IC-II Signal Levels Supported.
MORPH-IC-II provides a flexible method to process signals of different voltage levels. This method allows a voltage of either 3.3V, 2.5V, 1.8V or 1.5V to be applied to I/O Bank 4 by adjusting the externally supplied power supply to bank 4 and reconfiguring the pin-map. This means MORPH-IC-II supports the different voltage levels on different banks as shown in Fig. 3. As illustrated in Fig. 3 I/O Banks 1 - 3 can only process 3.3V TTL and CMOS signals. Other voltage levels are not supported on these I/O banks since signal lines between FT2232H and FPGA are connected to these I/Os. Therefore a 3.3V power supply is hardwired to the voltage supplies of I/O Bank 1-3. A step by step example of how to modify the I/O signal levels of I/O Bank 4 is given in a separate applications note "AN_141_MorphIO-II and MorphLd Utilities for Morphic-II". This can be downloaded from the FTDI website.
I/O Bank 2 3V3
3V3
All I/O Banks Support 3.3-V LVTTL/LVCMOS I/O Bank 1 Only I/O Bank 4 Support 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS I/O Bank 3
3V3
Individual Power Bus
1V5 / 1V8 / 2V5 /3V3
I/O Bank 4
Fig. 3 - I/O Bank Logic Voltage Levels
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
3.4 MORPH-IC-II Header Connections.
MORPH-IC-IIs FPGA is connected to five connectors: J1-J4 and the JTAG Port. J1 to J4 are used for the following functions: connecting I/Os, "self-powered" power supply, specific bank supply voltages and clock connections. The JTAG connector is used to scan the I/O and registers of the FPGA.
Reference Designator J1 J2 J3 J4 CN1
Name JTAG Port
Description 40 Pin Header 40 Pin Header 24 Pin Header 24 Pin Header USB Connector JTAG Port, used to scan I/Os and registers of the FPGA, this feature makes it possible to probe of the signals of a FPGA.
CN2
Table 2 - Connector Description
A description for each MORPH-IC-II connector is given in Table 2. The pin description of J1, J2, J3 and J4 connectors are given in Table 3, Table 4, Table 5 and Table 6. Pin labels for these headers are also illustrated in Fig 4 and Fig 5.
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
Connector Pin
Name
Description When Jumper VBUS is closed J1-1 outputs the USB Bus Voltage, When Jumper VBUS is open J1-1 is an input for and external power supply to the board.
Connector Pin
Name
Description
J1-1
VCCUSB
J1-21
IOR3
General Input/output
J1-2 J1-3 J1-4 J1-5 J1-6 J1-7
VCCSW AD4 AD5 AD6 AD7 TXE#
5V Power pin, turned off during USB suspend Data Transfer Interface Data Transfer Interface Data Transfer Interface Data Transfer Interface Data Transfer Interface (Active Low) Data Transfer Interface (Active Low) Data Transfer Interface (Active Low) Data Transfer Interface (Active Low) 0V Power pin 0V Power pin General Input/Output Reset Input (Active Low) General Input/Output General Input/Output 3.3V Power pin, turned off during USB suspend 3.3V Power pin, turned off during USB suspend General Input/Output General Input/Output
J1-22 J1-23 J1-24 J1-25 J1-26 J1-27
IOL3 GND GND IOL4 IOM4 IOP4
General Input/output 0V Power pin 0V Power pin General Input/output General Input/output General Input/output
J1-8
RXF#
J1-28
IOK4
General Input/Output 3.3V Power pin, turned off during USB suspend 3.3V Power pin, turned off during USB suspend General Input/Output General Input/Output General Input/Output General Input/Output 0V Power pin 0V Power pin No Connection
J1-9
WR#
J1-29
3V3IO
J1-10 J1-11 J1-12 J1-13 J1-14 J1-15 J1-16 J1-17
RD# GND GND IOK1 RESETIN# IOP11 IOC1 3V3IO
J1-30 J1-31 J1-32 J1-33 J1-34 J1-35 J1-36 J1-37
3V3IO IOP5 IOK5 IOR7 ION8 GND GND NC
J1-18 J1-19 J1-20
3V3IO IOT4 IOT7
J1-38 J1-39 J1-40
IOR8 IOL9 IOM11
General Input/Output General Input/Output General Input/Output
Table 3 - Pin out of Connection J1
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Connector Pin J2-1 J2-2 J2-3 J2-4 J2-5 J2-6 J2-7 J2-8 J2-9 Connector Pin J2-21 J2-22 J2-23 J2-24 J2-25 J2-26 J2-27 J2-28 J2-29
Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
Name AD3 AD2 AD0 AD1 NC NC IOE4 IOE3 IOE5
Description Data Transfer Interface Data Transfer Interface Data Transfer Interface Data Transfer Interface No Connection No Connection General Input/Output General Input/Output General Input/Output
Name IOA6 IOB7 GND GND IOG7 IOA9 IOG6 IOF6 V_BANK4
Description General Input/Output General Input/Output 0V Power pin 0V Power pin General Input/Output General Input/Output General Input/Output General Input/Output 3.3V Power pin/V-Bank 4 power supply 3.3V Power pin/V-Bank 4 power supply General Input/Output General Input/Output General Input/Output General Input/Output 0V Power pin 0V Power pin
J2-10 J2-11 J2-12 J2-13 J2-14 J2-15 J2-16
IOD4 GND GND IOA7 CLKIN IOA3 GND
General Input/Output 0V Power pin 0V Power pin General Input/Output Secondary input clock source General Input/Output General Input/Output
J2-30 J2-31 J2-32 J2-33 J2-34 J2-35 J2-36
V_BANK4 IOD5 IOC5 IOE6 IOD8 GND GND
J2-17
3V3IO
3.3V Power pin, turned off during USB suspend
J2-37
IOF9
General Input/Output
J2-18 J2-19 J2-20
3V3IO IOA5 IOD6
3.3V Power pin, turned off during USB suspend General Input/Output General Input/Output
J2-38 J2-39 J2-40
IOC11 IOC12 IOC13
General Input/Output General Input/Output General Input/Output
Table 4 - Pin out of Connection J2
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
Connector Pin J3-1
Name
Description 3.3V Power pin, turned off during USB suspend 3.3V Power pin, turned off during USB suspend General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output
Connector Pin J3-13
Name
Description
3V3IO
IOR14
General Input/Output
J3-2 J3-3 J3-4 J3-5 J3-6 J3-7 J3-8 J3-9 J3-10 J3-11 J3-12
3V3IO ION11 IOP13 IOL12 IOT9 IOR9 IOT10 IOR11 IOT13 IOR13 IOT14
J3-14 J3-15 J3-16 J3-17 J3-18 J3-19 J3-20 J3-21 J3-22 J3-23 J3-24
ION14 IOP16 IOP15 ION16 IOM14 IOL16 IOL15 IOK16 IOF16 JTAG_TDI JTAG_TMS
General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output JTAG Interface JTAG Interface
Table 5 - Pin out of Connection J3
Connector Pin J4-1 J4-2 J4-3 J4-4 J4-5 J4-6 J4-7 J4-8 J4-9 J4-10 J4-11 J4-12
Name IOF15 IOD13 IOH13 IOD14 IOG12 IOG13 IOJ11 IOC14 IOJ12 IOG16 IOB12 IOA12
Description General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output
Connector Pin J4-13 J3-14 J4-15 J4-16 J4-17 J4-18 J4-19 J4-20 J4-21 J4-22 J4-23 J4-24
Name IOB13 IOA13 IOB14 IOA14 IOD15 IOD16 IOE14 IOE16 GND GND JTAG_TDO JTAG_TCK
Description General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output General Input/Output 0V Power pin 0V Power pin JTAG Interface JTAG Interface
Table 6 - Pin out of Connection J4
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
Morph-IC II Pin-out J1 (Top View) VCCUSB AD4 AD6 TXE# WR# GND IOK1 IOP11 3V3IO IOT4 IOR3 GND IOL4 IOP4 3V3IO IOP5 IOR7 GND NC IOL9
1 2
Fixed Voltage Lines
Variable Voltage Lines
Morph-IC II Pin-out J2 (Top View)
1 2
VCCSW AD5 AD7 RXF# RD# GND RESETIN# IOC1 3V3IO IOT7 IOL3 GND IOM4 IOK4 3V3IO IOK5 ION8 GND IOR8 IOM11
AD3 AD0 NC IOE4 IOE5 GND IOA7 IOA3 3V3IO IOA5 IOA6 GND IOG7 IOG6 V_BANK4 IOD5 IOE6 GND IOF9 IOC12
AD2 AD1 NC IOE3 IOD4 GND CLKIN GND 3V3IO IOD6 IOB7 GND IOA9 IOF6 V_BANK4 IOC5 IOD8 GND IOC11 IOC13
3
4
3
4
5
6
5
6
7
8
7
8
9
10
9
10
11
12
11
12
13
14
13
14
15
16
15
16
17
18
17
18
19
20
19
20
21
22
21
22
23
24
23
24
25
26
25
26
27
28
27
28
29
30
29
30
31
32
31
32
33
34
33
34
35
36
35
36
37
38
37
38
39
40
39
40
Fig. 4 - Pin outs of J1 & J2
# = Active Low The signal names of J1 and J2 are illustrated in Fig. 4. The pins are colour coded to indicate whether or not the pin is associated with I/O BANK4. Likewise Fig. 5 defines the pins associated with the variable voltage level tolerant I/O BANK4. Fig 5 also details labelling of J3 and J4 signals.
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
Morph-IC II Pin-out J3 (Top View) 3V3IO ION11 IOL12 IOR9 IOR11 IOR13 IOR14 IOP16 ION16 IOL16 IOK16 JTAG_TDI
1 2
Fixed Voltage Lines
Variable Voltage Lines
Morph-IC II Pin-out J4 (Top View)
1 2
3V3IO IOP13 IOT9 IOT10 IOT13 IOT14 ION14 IOP15 IOM14 IOL15 IOF16 JTAG_TMS
IOF15 IOH13 IOG12 IOJ11 IOJ12 IOB12 IOB13 IOB14 IOD15 IOE14 GND JTAG_TDO
IOD13 IOD14 IOG13 IOC14 IOG16 IOA12 IOA13 IOA14 IOD16 IOE16 GND JTAG_TCK
3
4
3
4
5
6
5
6
7
8
7
8
9
10
9
10
11
12
11
12
13
14
13
14
15
16
15
16
17
18
17
18
19
20
19
20
21
22
21
22
23
24
23
24
Fig. 5 - Pin outs of J3 & J4
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
3.5 MORPH-IC-II Hardware Configuration
3.5.1 Communications and Programming Interfaces of MORPH-IC-II
MORPH-IC-II communicates with a PC via USB. To allow USB communications between a PC and the FPGA, MORPH-IC-II uses an FT2232H USB device to create a communications bridge between the PC USB interface and the FPGA. This communications bridge splits into two channels: a programming interface channel and a parallel 245 FIFO communications interface channel. The programming interface uses channel B of the FT2232H to configure the FPGA using Alteras Passive Serial interface. The 245 communications interface uses channel A of the FT2232H to transfer data, either synchronously or asynchronously, over the 245 FIFO interface to and from the FPGA. The connections of the programming interface are illustrated in Fig. 6 and the connections of the 245 FIFO data interface are illustrated in Fig. 7. For synchronous 245 FIFO mode two extra data lines are required; these are CLKOUT and OE# (Output Enable). These two additional signals provide the synchronous clock and control line for the synchronous 245 mode. This mode can transmit data at higher rates than asynchronous 245 FIFO. These signals are only available on channel A of the FT2232H chip therefore; MORPH-IC-II uses channel A for the FIFO interface as opposed to MorphIC-1K which has the FIFO interface in channel B. This leaves channel B available on MORPH-IC-II to be used to program the FPGA. This difference does not affect backward compatibility with MorphIC-1K hardware, but this change needs to be considered when upgrading a MorphIC-1K application to a MORPH-IC-II application. MORPH-IC-II utilises the functionality of the Multi-Protocol Synchronous Serial Engine (MPSSE) architecture in channel B of the FT2232H chip to adapt to the Alteras Passive Serial interface. MPSSE is an FTDI function that allows different synchronous protocols to be configured on any available data channel. Once the FPGA has been configured, channel B of FT2232H can be reconfigured, using MPSSE, to operate as general purpose IO pins (see Section 3.5.2 for details on GPIO). The FPGA can be configured and reconfigured in less than 0.1 of a second. This provides flexibility for any application to be reconfigured on-the-fly. The FPGA configuration file (*.RBF or Raw Binary File) is output by Altera Quartus II software. These configuration files can then be downloaded to the FPGA using a *.RBF loading utility called the MorphLd which is included in the MORPH-IC-II package. Alternatively, for on-the-fly programming, application software can be used to load *.RBFs using commands driven by FTDIs DLL library. An example of where a software programme executed a load *.RBF file command is the MorphIO-II utility where the utility is set to run an *.RBF containing the HDL code designed for this programme is loaded to the FPGA More information and instructions on how to use these utilities are given in application note AN_141_MorphIO-II and MorphLd Utilities for MORPH-IC-II.
Programming Interface
38 39
TCK DCLK
H4
TDI DATA0 TDO NCONFIG
F1
USB
FT2232HQ USB INTERFACE I.C
40
J5
41
TMS NSTATUS GPIOL0 CONF_DONE
M13 L13
ALTERA CYCLONE II EP2C5F256C8N FPGA
43
46
GPIOL3 DATA3
B3
Fig. 6 - The Passive Serial Programming Interface
Copyright (c) 2010 Future Technology Devices International Limited
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
Communications Interface
16 16 AD0 IO E2 E2
17 17
AD1
IO
E1 E1
18 18
AD2
IO
D3 D3
19 19
AD3
IO
F3 F3
21 21
AD4
IO
P2 P2
22 22
AD5
IO
P1 P1
23 23
AD6
IO
M4 N2 ALTERA CYCLONE II EP2C5F256C8N FPGA
USB
FT2232HQ USB INTERFACE
24 24 26 26
AD7
IO
N1 N1
RXF#
IO
M2 M2
27 27
TXE#
IO
M1 M1
28 28
RD#
IO
L2 L2
29 29
WR#
IO
J4 J4
30 30 32 32 33 33
SI/WUB CLKOUT OE#
IO IO IO
L1 L1 J2 J2 K2 K2
Fig. 7 - The 245 Communication Interface
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
3.5.2 GPIO Connections
The programming interface used by channel B of FT2232H is outlined at the beginning of section 3.5. Once the FPGA has been programmed, channel B of FT2232H can be redefined to utilise the six GPIO connections to the FPGA. These GPIO connections are illustrated in Fig. 8.
GPIO Connections
44 45
BB1
A8 A4
BB2
USB
FT2232HQ USB INTERFACE I.C
48
BB3
B4
54
BB4
B11 A11
ALTERA CYCLONE II EP2C5F256C8N FPGA
58
BB5
59
BB6
B9
Fig. 8 - GPIO Connections
3.5.3 MORPH-IC-II JTAG Connections
The interface between a JTAG programmer and MORPH-IC-IIs JTAG interface is illustrated in Fig. 9. The block on the left represents a programmer that will interface with the MORPH-IC-II. The block on the right represents the MORPH-IC-II FPGA module.
JTAG TDI
JTAG TDI
JTAG TDO
JTAG TDO
JTAG TMS
JTAG TMS
JTAG TCK
JTAG TCK
JTAG Programmer
Morphic-II
Fig. 9 - JTAG Programmer Interface
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
3.5.4 Pin-Map Configuration
The Cyclone-II FPGA of the MORPH-IC-II can be configured from an *.RBF file. These *.RBF files can be generated using the free software package called Quartus II. An *.RBF file generated by Quartus II contains the *.RTL code which synthesises the circuit, the signals of each pin (which are defined in the top level entity of the *.RTL) and the settings of each pin (which includes current draw and logic level standards). The pin map editor included in Quartus-II is used to specify the signal assignments and the setting of each pin. Along with making pin assignment to each port of the top-level entity, the voltage and current can be defined for each port. However there are restrictions, every signal in an I/O Bank needs to operate at the same logic voltage level and the I/O Bank needs to be powered with the same voltage as the logic voltage level of the signals. MORPH-IC-IIs I/O Banks 1 to 3 are connected directly to the FT2232H chip and all these signals are fixed to 3.3V-TTL/CMOS. I/O Bank 4 is the only bank that can have signals operating at voltages other than 3.3V-TTL/CMOS. Again all signals need to be at the same logic voltage level, to supply power with a voltage other than 3.3V, remove V_BANK4 jumper and apply DC power regulated to the same voltage level as the logic voltage level of I/O Bank4 to (at least one of) the header nodes labelled V_BANK4. More information and an example for pin-map editing are given in the application note: AN_141_MorphIO-II and MorphLd Utilities for MORPH-IC-II
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
4
MorphIO-II - An Application Software
MorphIO-II is an easy to use utility used for displaying and setting the binary levels and port direction of all MORPH-IC-IIs 80 I/Os. A screen shot demonstrating how the IO are set is given in Fig. 10. This diagram shows MorphIO-II with some voltage levels set to different values. An illustration of J1-19 being set to low and J1-15 being set to high is also shown here. It is also illustrated that only these two pins are set as outputs the remaining pins are set as inputs. To set the level of a pin it is required to be defined as an output. The defined settings for a pin are illustrated in MorphIO-IIs GUI using a check box. These check boxes are located in one of the following columns I, O, H and L. Check boxes in the I columns set a pin to be an input. Check boxes in the O columns set a pin to be an output. Check boxes in the H columns set output pins to be high. Check boxes in the L columns set output pins to be low. It is also demonstrated in Fig. 11 pin J1-19 being set to a logic low thus inducing a logic low reading on this pin, all other levels read are logic highs. This is indicated by a green and red "light" around the level select check box which is used to display a logic level read of the pin, a green light indicates a low and red light indicates a high. In this demonstration J1-15 is set to output logic high, and it reads back logic high, while all other pins except pin J1-19 are reading logic high and are set to be inputs. All input pins are reading a logic high by default, this is because the I/Os of the Cyclone-II have a weak pull-up embedded in the FPGA. A screen shot of the entire MorphIO-II is illustrated in Fig. 11, all 80 I/O controls and clock enables are controlled through this GUI. A load and save configuration control is also displayed in this diagram; these controls are for controlling the feature used to save and load the settings all the controls of the MorphIOII. MorphIO-II can also be used to apply a clock signal to the dedicated clock pins of the FPGA, these dedicated clock pins are displayed on MorphIO-IIs GUI with a clock button next to the IO control panel. The frequency of the applied clock signal can range from 12.3KHz to 50MHz. An illustration of how to set the clock frequency is given in Fig. 12. The frequency is selected by navigating through the Setup tab, selecting the pin being toggled and selecting the required clock frequency. In MorphIO-IIs GUI, the I/O control blocks of I/O Bank 4 are colour coded dark gray to indicate that these I/Os can transfer signals with logic voltage levels other than 3.3V. In order to process these signals, two changes are necessary. The first change is to set the Quartus-II files used to configure MorphIO-IIs application to deal with these new I/O settings which are intended to be processed on I/O Bank4. This task is carried out by changing the I/O Standards specified in the I/O pin map for all ports in I/O Bank4 to be set to the IO Standard of the intended signal being processed via I/O Bank4. Then compile the new design and paste the newly generated *.RBF file to the directory of MorphIO-II making sure the name is "morphio50m_Mii" (MorphIO-II is hardcoded to read a *.RBF file with the name "morphio50m_Mii" from its stored directory). The second change is to reconfigure the hardware to supply the correct voltage to I/O Bank4, this is done by opening jumper VBank4 to remove the short to 3.3V, and then applying power with the voltage set to the same voltage as logic high of the used logic standard.
Fig. 10 - MorphIO-II Settings Copyright (c) 2010 Future Technology Devices International Limited 18

Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
Fig. 11 - MorphIO-II User Interface
Fig. 12 - Set Clock Frequency
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
5
Electrical Details
5.1 Absolute Maximum Ratings
The absolute maximum ratings of MORPH-IC-II are as follows. Exceeding these values may cause permanent damage to the device.
Parameter Storage Temperature Ambient Operating Temperature (Power Applied) DC Input Voltage - USBDP and USBDM DC Input Voltage - All Other Inputs such as PWREN#, SUSPEND#, RESET#, EECS, EECLK, EEDATA DC Input Voltage DC Output Current - Outputs from the FT2232H DC Output Current - Outputs from the FPGA VCCUSB - Self Powered Source EXT. VIO Value -65C to 150C 0C to 85C -0.5 to +3.63 -0.5 to + (VCC3V3 +0.5) -0.3 to +4.6 16 -25 to 40 -0.3 to 12 Unit Degrees C Degrees C V V V mA mA V V
-0.5 to 4.6 Table 5.1 - Absolute Maximum Ratings
5.2 Recommended Opperating Conditions
Parameter EXT. VIO - Supply voltage for output buffers, 3.3-V operation EXT. VIO - Supply voltage for output buffers, 2.5-V operation EXT. VIO - Supply voltage for output buffers, 1.8-V operation EXT. VIO - Supply voltage for output Value Unit
3.135 to 3.465
V
2.375 to 2.625
V
1.71 to 1.89
V
1.425 to 1.575 buffers, 1.5-V operation Table 5.2 - Recommended Operating Conditions
V
Description
VIL MAX
VIH MIN
VOL MAX 0.4 (LVTTL) 0.2 (LVCMOS) 0.4 0.45 0.25 x EXT. VIO
VOH MIN 2.4 (LVTTL) EXT. VIO - 0.2 (LVCMOS) 2.0 EXT. VIO - 0.45 0.75 x EXT. VIO
Unit
3.3V LVTTL and CMOS 2.5V LVTTL and CMOS 1.8V LVTTL and CMOS 1.5V LVTTL and CMOS
0.8 0.7 0.35 x EXT. VIO 0.35 x EXT. VIO
1.7 1.7 0.65 x EXT. VIO 0.65 x EXT. VIO
V V V V
Table 5.3 - Recommended Operating Conditions
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The I/O pins are +3.3v cells, which are +5V tolerant.
Parameter Vil Vih Vt VtVt+ Rpu Rpd RCONT Description Input low Switching Threshold Input High Switching Threshold Switching Threshold Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage Input pull-up resistance 2.00 Minimum Typical 1.50 0.80 1.10 1.60 2.00 Maximum 0.80
Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
Units V V V V V
Conditions LVTTL LVTTL LVTTL
40 75 190 K Input pull-down 40 75 190 K resistance Value of I/O pin pull-up resistor of FPGA before 10 25 50 K and during configuration Table 5.4 - I/O Pin Characteristics VCCIO = +3.3V
Vin = 0 Vin =VCCIO VCCIO = 3.3V
Detailed electrical characteristics of the FT2232H can be found in its datasheet at http://www.ftdichip.com/Documents/DataSheets.htm#ICs. Detailed electrical characteristics and ratings of the FPGA can be found in the Cyclone II handbook. This handbook can be found at http://www.altera.com/products/devices/cyclone2/cy2-index.jsp.
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
6
Mechanical Details
The mechanical details of MORPH-IC-II are illustrated in Fig. 13.
39.6mm 25.8mm 13.8mm
5.08mm 65.1mm 70.1mm
2.54mm
98.1mm 99.8mm
10mm
2.0mm 6mm 8.5mm
15mm
16.8mm
Fig. 13 - MORPH-IC-II Dimensions (Top and Side View)
All dimensions shown in millimetres with a tolerance of 0.1mm. The headers J1, J2, J3 and J4 are mounted on the bottom of the PCB. The overall height (top of USB connector to bottom of pins) of the module is 18.5mm. The cross section of each pin is 0.64 mm square.
Copyright (c) 2010 Future Technology Devices International Limited
2.54mm
37.6mm 30.48mm
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Document Reference No.: FT_000198 MORPH-IC-II Datasheet Version 1.02 Clearance No.: FTDI# 164
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Contact Information
Head Office - Glasgow, UK
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Branch Office - Taipei, Taiwan
Future Technology Devices International Limited (Taiwan) 2F, No. 516, Sec. 1, NeiHu Road Taipei 114 Taiwan , R.O.C. Tel: +886 (0) 2 8797 1330 Fax: +886 (0) 2 8751 9737 E-mail (Sales) E-mail (Support) E-mail (General Enquiries) Web Site URL tw.sales1@ftdichip.com tw.support1@ftdichip.com tw.admin1@ftdichip.com http://www.ftdichip.com
Branch Office - Hillsboro, Oregon, USA
Future Technology Devices International Limited (USA) 7235 NW Evergreen Parkway, Suite 600 Hillsboro, OR 97123-5803 USA Tel: +1 (503) 547 0988 Fax: +1 (503) 547 0987 E-Mail (Sales) E-mail (Support) E-mail (General Enquiries) Web Site URL us.sales@ftdichip.com us.support@ftdichip.com us.admin@ftdichip.com http://www.ftdichip.com
Branch Office - ShangHai, China
Future Technology Devices International Limited (China) Room 408, 317 Xianxia Road, ChangNing District, ShangHai, P.R. China Tel: +86 (21) 62351596 Fax: +86 (21) 62351595 E-Mail (Sales) E-mail (Support) E-Mail (General Enquiries) Web Site URL cn.sales@ftdichip.com cn.support@ftdichip.com cn.admin@ftdichip.com http://www.ftdichip.com
Distributor and Sales Representatives
Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales representative(s) in your country.
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Appendix A - FT2232H EEPROM Configuration
The MORPH-IC-II utilises an EEPROM which contains the USB configuration descriptors for the FT2232H. When this module is plugged into a PC or a USB reset is performed, the PC will read these descriptors. The default values stored into the EEPROM are defined in Table 5.
Parameter USB Vendor ID (VID) USB Product UD (PID) Serial Number Enabled? Serial Number Pull down I/O Pins in USB Suspend Manufacturer Name Product Description Max Bus Power Current Power Source USB Version Remote Wake Up Load VCP Driver
Value 0403h 6010h Yes See Note
Notes FTDI default VID (hex) FTDI default PID (hex)
A unique serial number is generated and programmed into the EEPROM during device final test. I/O pins on the FT2232H are pulled high during USB Suspend (PWREN# is high).
Disabled FTDI MORPH-IC-II 500mA Bus Powered 0200 Disabled Disabled
Hi-Speed USB Remote Wake Up is disabled The MORPH-IC-II will only load the D2XX device driver. The loading of VCP ports is suppressed.
Table 5 - Default Internal EEPROM Configuration
The EEPROM on the MORPH-IC-II can be re-programmed over USB using the utility program MPROG or FT_PROG. Both can be downloaded from the www.ftdichip.com. MPROG Version 3.5 or later is required for the FT2232H chip. Users who do not have their own USB Vendor ID but would like to use a unique Product ID in their design can apply to FTDI for a free block of unique PIDs. Contact FTDI support for this service.
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Appendix B - Revision History
Draft Rev 1.0 Rev 1.01 Rev 1.02 First draft First release Minor text corrections Updated max speed to 40Mbytes/s due to new driver 28th October 2009 9th August 2010 20th August 2010 26th August 2010
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Appendix C - Schematic Drawings
Fig. 14 - A Schematic of the USB Interface
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Fig. 15 - A Schematic of the FPGA
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Fig. 16 - A Schematic of the I/O Pin
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Appendix D - Assembly Drawings
Fig. 17 - Component Layout Top View
Fig. 18 - Component Layout Bottom View
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